## Ohmic Or Linear Region

Biasing JFET we will learn about the different biasing techniques for the JFET. And in this particular article, we will learn about the fixed bias configuration. But before we do that, first of all, let’s understand what do we mean by bias.

Biasing JFET And to understand that let’s quickly see what we had seen in the last couple of Articles. So, in the previous article, we had seen the output and the transfer characteristics of the JFET. And then we had discussed the different regions of operation for the JFET.

For example, whenever the JFET is operated in this particular region, then it is known as either the ohmic or triode region of operation. Biasing JFET And in this region, the JFET works as a variable resistor. So, to operate the n-channel JFET in this region, Vds should be less than Vgs – Vp. And of course, the value of Vgs should be between this 0 and the pinch-off voltage.

So, when this condition is satisfied then the JFET will operate in this ohmic region. And similarly, for the p-channel JFET, Biasing JFET the magnitude of Vds should be less than Vp – Vgs. Because, in the case of the p-channel JFET, both Vp and Vgs are positive. And in this linear region.

the drain current is the function of both voltage** Vds and the voltage Vgs.** And the drain current Id can be given by this expression. And then after we had seen the **saturation or the active region of the JFET.**

So, in this region, the JFET can be used for the linear amplification of the AC signal.

And to operate the JFET in this region, the value of voltage Vds should be on the right-hand side of this parabolic curve. Or mathematically we can say that the value of voltage Vds should be greater than or equal to **Vgs – Vp Biasing JFET. **

And similarly for the **p-channel JFET,** the magnitude of the voltage Vds, should be greater than or equal to **Vp – Vgs.** So, once this condition is satisfied then the JFET will operate in the saturation region.

Also Read: Crystal Oscillator Explained

**Saturation Region** & Active Region

in this **saturation region**, the drain current can be given by this expression. So, then after we had seen the **cut-off region of operation.** So, in this region of operation, the drain current Id is almost zero Biasing JFET.

## Cut-Off Region

So, to operate the JFET in this region, for the** n-channel JFET**, the value of voltage Vgs should be less than or equal to **Vp**. Or in other words, we can say that whenever the voltage Vgs is more negative than this pinch-off voltage, then** the JFET** will operate in this **cut-off region.**

And similarly, for the **p-channel JFET**, this voltage Vgs should be more than this pinch-off voltage Vp. So, once this condition is satisfied then the **JFET** will operate in the **cut-off region.**

Also Read: Colpitts Oscillator Explained

## JFET As Switch

operating the JFET in the saturation and the cut-off region, it can be used as a switch. So, whenever the JFET is operating in the saturation region, then it will act as a closed switch. And whenever it is operating in the cut-off region, then it will act as an open switch Biasing JFET.

So, in this way, by operating the JFET in the different regions, it can be used for various applications. But to operate the JFET for the various applications, the operating point of the JFET should be selected properly. Biasing JFET And here, the operating point defines the value of drain current Id and voltage Vds.

Also Read: Wien Bridge Oscillator (using op-amp) Explained

## JFET Biasing

So, biasing is the process of selecting the operating voltage and the current of JFET such that it should operate in the specific region. And doing so, it can be used for the specific application.

And there are three different biasing techniques that are used for the JFET. which are Fixed Bias, Self Bias, and the voltage divider Bias Biasing JFET.

## JFET Fixed Bias Configuration.

And in this particular article, we will learn about the Fixed Bias Configuration. So, the circuit diagram which is shown in the figure is the Fixed Bias configuration of the JFET which is used for the amplification of the AC signal. So, as you can see over here, Biasing JFET a small input signal is applied through this input coupling capacitor Ci, and the output is measured between this drain and the source terminal via this coupling capacitor Cout. And here the biasing voltage and the current for the circuit are set using these two resistors and the voltage sources.

Now, here we are only interested in the dc operating point of the given circuit. Or in other words, we can say that we are interested in the DC analysis of the circuit. So, for the DC analysis, we can consider all the AC sources as zero and we can consider all the coupling capacitors as an open circuit.

So, for the DC analysis of the circuit, the equivalent circuit will look like this. Now, for the JFET, the input impedance of this gate terminal is very high. Or we can say that this gate current Ig is approximately equal to 0.

So, if that is the case, then there will not be any flow of current through this gate terminal. And due to that, we can say that there will not be any voltage drop across this resistor Rg. So, in the equivalent circuit, this resistor will act as a short circuit. And considering this point, the equivalent circuit will look like this. So, for the given circuit, now we are interested in finding the drain current Id and the voltage between this drain and the source terminal.

So, let’s see, how we can find this drain current Id and the voltage between this drain and the source terminal. But before that first of all, let’s find out the voltage between this gate and the source terminal. Now, if you observe over here, the source terminal is already grounded. So, if we apply the KVL for this loop, then we can write it as, Vgs = -Vgg. So, this voltage is appearing between the gate and the source terminal. And from this voltage, we can find the drain current.

So, we had seen that the drain current is given as Idss x (1- Vgs/Vp)^2But this expression is valid whenever the JFET is operated in the saturation region. So, here let’s assume that the JFET is used as an amplifier and it is already operated in the saturation region. So, considering this we can use this expression. And from this expression, we can find the value of the current Id.

And once we know the value of this drain current, then we can easily find the voltage Vds by applying the KVL in this outer loop. So, let’s apply the KVL in the outer loop, and let’s find out the expression for this voltage Vds.

So, for the given circuit, let’s say due to this drain current Id, the voltage drop across this resistor Rd is equal to Vrd. And the voltage drop between this drain and the source terminal is equal to Vds. So, applying the KVL in the outer loop, we can write Vdd – Vrd – Vds = 0 Or we can say that this voltage Vds is equal to Vdd- Vrd.

And here, Vrd can be written as, Id timesRd. So, this is the expression of the voltage Vds in terms of the drain current Id. So, in this way, we can find the drain current and the voltage Vds for the given JFET. Or in other words, we can find the operating point of the given JFET.

Also Read: Wien Bridge Oscillator (using op-amp) Explained