Hey friends, welcome to Kohiki.com In the previous article, we have seen that what is **Field Effect Transistor.** And then we have briefly discussed the different types of FETs. So, in this article, we will learn about the **JFET **in detail. And we will see the construction as well as the working of this **JFET.** Now, in the previous article we have seen that in the case of a **field effect transistor**, the path through which the charge carrier flows is **known as channel FET.**

**Field Effect Transistor**

- if this channel is made up of n-type material then the
**field-effect**transistor is known as the n-channel FET. - likewise, if the channel is made up of p-type semiconductor material, then the field-effect
**transistor**is known as the**p-channel****FET**. - So, in the case of
**n-channel**JFET, the channel is made up of n-type material. And two small p-type regions are fabricated near this channel.

## Junction Field Effect Transistor or JFET

if you see the structure, this n-type material is the major part of the entire structure. So, through the ohmic contact, the top of the **n-channel **is connected to the drain terminal and the bottom of the n-channel is connected to the source terminal. And two p-type regions are connected together to the gate terminal. So, in this n-channel **JFET**, due to this p-type, regions two **p-n junctions** are formed. And due to that, the depletion region is also formed near this junction.

Now, whenever we apply the voltage between the drain and the source terminal, then the current starts flowing through the device between the drain and the source terminal. And by applying the voltage between this gate and the source terminal, this current can be controlled. So, the working of the JFET can be explained using the tap-water analogy.

So, as we know, in the case of a tap-water the water flows from the source towards the drain. And the flow of water can be controlled using this knob. So, similarly, in the case of this **FET**, the voltage between this gate and the source terminal controls the current which is flowing between the drain and the source terminal. So, now let’s exactly see how this JFET works by taking the example of the **n-channel** **FET**. And let’s also see what should be the exact polarity of the voltages between this drain and the source as well as between the gate and the source terminal.

- So, first of all, let’s assume that this gate and the source terminals are connected together.
- So, as you can see over here, the source terminal is connected to the ground and the gate and the source terminals are connected together.
- Now, here in the case of this
**n-channel**JFET, the voltage between this drain and the source terminal should be positive. - So, here let’s say this voltage Vdd is applied between this drain and the source terminal.
- So, this voltage Vds should be positive. That means the drain terminal should be more positive than this source terminal.
- So, now once we apply this voltage then the electrons start flowing from the source terminal to the drain terminal.

And if we see the conventional current, then the current starts flowing from the drain terminal towards the source terminal. so, here let’s say Id is the current which is flowing into the drain terminal. And the Is is current which is flowing out of the source terminal. And as you can see, this current Id is equal to Is.

- So, instead of defining these two currents as a separate current, we will only define this drain current Id.
- So, now considering this Vgs is equal to zero and Vds is positive, let’s see how this n-channel
**JFET works**. - So, whenever this Vds is positive, then these two PN junctions will become reversed biased. And due to this reverse bias connection, the width of the depletion region will increase.
- Now, if you notice over here, the depletion region is wider at the top of this p-type region.
- it is narrower at the bottom of this p-type region. So, first of all, let’s understand the reason behind it.
- Now, during the operation, this n-channel acts like a resistor.
- let’s assume, the uniform resistance throughout this n-channel.
- So, this n-channel can be modeled as a series of distributed resistors between the drain and the source terminal.
- whenever this drain current Id flows, then there will be a voltage drop across each resistor.

So, let’s say the voltage at the top end is equal to 2V. And as we move towards the source terminal then there will be a voltage drop across each resistor. And due to that, the upper region of the **p-type material** will be more reverse-biased compared to the lower region. And we had seen in the earlier article, as we increase the applied reverse bias voltage, the width of the depletion region will increase.

So, due to that, the depletion region is wider at the top portion. And it is narrow at the bottom portion. So, in short, due to the applied voltage Vdd, these two PN junctions will become reversed biased. And due to that only a small amount of reverse saturation current will flow through this PN junction. And for the practical cases, we can consider that the current Ig through this gate terminal is equal to zero. So, due to these reverse-biased PN junctions, the input impedance of this JFET is very high. So, now as we increase this voltage Vds from zero to a few volts, then the current which is flowing through the channel will increase.

If we plot this current Id versus Vds, then initially it will almost look like a straight line. So, this curve of Id vs Vds is known as the output characteristic of this JFET. Or sometimes it is also known as the drain curves for the JFET. So, as you can see, for the low voltages, this curve is an almost straight line. Meaning that for the low voltages, the resistance of the channel remains constant. But if we keep on increasing this voltage Vds then the width of the depletion region will become wider.

due to that, the channel will become narrower and narrower. So, due to this reduced channel width, now the channel resistance will increase. And that is also evident from the graph. So, if you see this region of the graph, the slope of the line changes and it becomes more and more horizontal. So, basically, it indicates that as we increase the voltage Vds, then the channel resistance will increase. And now if we further increase the voltage Vds, then at one particular voltage, the depletion regions will touch each other.

## N-Channel JFET Output Characteristic

if we plot this current Id versus Vds, then initially it will almost look like a straight line. So, this curve of Id vs Vds is known as the output characteristic of this JFET. Or sometimes it is also known as the drain curves for the JFET. So, as you can see, for the low voltages, this curve is an almost straight line. Meaning that for the low voltages, the resistance of the channel remains constant. But if we keep on increasing this voltage Vds then the width of the depletion region will become wider. And due to that, the channel will become narrower and narrower.

So, due to this reduced channel width, now the channel resistance will increase. And that is also evident from the graph. So, if you see this region of the graph, the slope of the line changes and it becomes more and more horizontal. So, basically, it indicates that as we increase the voltage Vds, then the channel resistance will increase.

## Pinch Off Condition In JFET

**now if we**further increase the voltage Vds, then at one particular voltage, the depletion regions will touch each other.- So, this condition is known as the pinch-off condition. And the voltage at which this occurs is known as the pinch-off voltage.
- So, let’s denote this pinch-off voltage as Vp.
- So, whenever this Vds is greater than or equal to Vp, then this pinch-off condition will occur.
- So, the name pinch-off suggests, once this condition occurs, then the current Id should drop to zero.
- Because now, there is no path for the charge carriers to flow from this side towards this side. But in reality, if you see, that is not the case.
- in fact, once the pinch-off condition is reached, the current Id reaches the saturation level. So, let’s understand why is it so.

So, first of all, let’s assume that once the pinch-off condition is reached, then this Id is equal to 0. So, if that is the case, then the absence of the drain current would remove the possibility of the different potential levels across this-channel. And due to that, the reverse bias across the PN junction would be removed. And that would result in the loss of the depletion region which causes the pinch-off in the first place.

So, basically, this current Id will not become zero. And in fact, at the pinch-off condition, this current Id is the maximum current. So, this saturation current is denoted asIdss. And Idss is the maximum current of the JFET

whenever the Vgs is equal to zero and Vds is more than pinch-off voltage. So, whenever this Vds is more than this pinch-off voltage then the current which is flowing through the device is almost constant. And in this region of operation, the JFETworks as a constant current source. So, basically, under this region of operation, we will get a constant current through this device. Now, so far in our discussion, we have assumed that the voltage Vgs is equal to zero. But as discussed earlier, this gate to source voltage can control this drain current.

So, now let’s see, how the voltage level ofVgs can control the drain current. Or in a way, how it can affect the drain curves or the output characteristic of this JFET. So, now what we will do, we will make these Vgs more and more negative with respect to zero volts. And we will find the drain currents for the different values of the Vgs.

## N-Channel JFET

So, first, let’s assume that the Vgs is equal to -1V. So, due to this negative voltage now the depletion region will get created across this PN junction.

And as we keep on increasing this voltage Vds, between the drain and the source terminal, then the width of the depletion region will increase. But now, the pinch-off condition or the saturation of the drain current will be reached at the lower voltage of Vds. Because due to this negative voltage of Vgs, the PN junction is already reverse biased. So, in case of this Vgs is equal to -1V, ifwe see the drain curve, then it will look like this. So, as you can see, at Vgs is equal to -1V,the saturation value of the drain current has been reduced. And in fact, it will continuously reduce,once we reduce the value of Vgs below this zero volt.

So, as you can see, if we reduce the value of Vgs, from -1V to -2V, then further this saturation value of the drain current will reduce. And whenever, this Vgs is equal to -Vp then the saturation current will essentially become zero. So, this region of operation is known as the cut-off region of operation. Or we can say that whenever this Vgs is equal to -Vp, at that time the device is turned off. So, in this way, this JFET can be operated in three different regions.

The ohmic region, the saturation region, and the cut-off region. So, in this ohmic region, the JFET will work as a resistor. And for the fixed value of Vgs, it provides almost constant resistance. But as we reduce the value of these Vgs, then the resistance of the channel will increase. So, basically in this region, the JFET can be operated as a variable resistor. And by changing the voltage between the gate and the source terminal, we can control the resistance of this JFET.

Then the second region of operation is the saturation region. So, in this region, whenever this drain to source voltage or Vds is more than this pinch-off voltage Vp, at that time the drain current will almost remain constant. And the third region of operation is the cut-off region. So, whenever this Vgs is greater than or equal to Vp at that time, this drains current Id will be approximately equal to 0. And we can say that the device is turned off. So, apart from these three regions, there is one more region. And it is known as the breakdown region. And like a diode, this region of operation should be avoided.

So, in this saturation region of operation, we increase this voltage Vds beyond a certain limit, then there is a vertical rise in this drain current. Or we can say that the breakdown has occurred. And now the current is limited solely by the external circuit. So, generally in the datasheet, the maximum value of the Vds has been defined.

So, during the operation, the value of these Vds should be less than this rated value. So, this all about the output characteristics or the drain curves of the JFET. Now, so far in our discussion, we have only discussed the n-channel JFET. But the p-channel JFET also works in a similar way.

## P-Channel JFET

So, in the case of this p-channel JFET, the channel is made up of a p-type semiconductor. And two small n-type regions are fabricated near this channel. And in the case of p-channel JFET, now the polarity of the biasing voltage also reversed. So, now in the case of this p-channel JFET, the drain to source voltage should be negative and the gate to source voltage should be positive. Apart from that in the case of this p-channel JFET, now the charge carriers will be holes. And when we apply the voltage between the rain and the source terminal, then they will start moving from the source towards the drain terminal.

## P-Channel JFET Output Characteristics

(1) Output or drain characteristic and

(2) Transfer characteristic.

So, now if we see the Id versus Vds curve or the output characteristics of the p-channel JFET, then it will look quite similar to then-channel JFET. But in this case, this voltage Vds is negative. That means if you see the voltages on this horizontal axis, they will be negative. So, now in the case of this p-channel JFET, as we increase the voltage Vgs, then the saturation value of the drain current will reduce.

And whenever this Vgs is equal to Vp, or the pinch-off voltage, then the drain current Id will be approximately equal to zero amperes. And similarly to the n-channel JFET, there is also a breakdown region in the case of this p-channel JFET. That means if we go beyond the certain value of this voltage Vds, then the drain current will increase drastically. So, this is all about the output characteristics of the p-channel JFET.

## Graphical Symbol JFET

Alright so now let’s see the electronic symbol of this n-channel as well as the **p-channel JFET. **So, these are the symbols of the n-channel and **p-channel JFET.** And if you see these symbols, **it has three terminals**. The gate, drain, and the source terminal. And in fact, if you see these two symbols, they almost look identical.

But the only difference between the two symbols is the direction of the arrow. So, in the case of an **n-channel JFET**, the arrow is going inwards.

While in the case of a p-channel **JFET**, the arrow is going outwards. And basically, these arrow indicates the direction of the flow of current whenever the PN junction is forward biased. So, in the case of p-channel **JFET**, whenever the PN junction is forward biased, then the current will flow in the outward direction.

While in the case of n-channel JFET, whenever the PN junction is forward biased, then the current will flow in the inward direction. And apart from these symbols, sometimes this symbol is also used for the n-channel and the p-channel **JFT.** So, I hope in this Article you understood the construction as well as the working of this **JFET**.

So, in the next article, we will find the relationship between the voltage Vgs and the drain current Id. And we will find the transfer characteristicsof this **JFET.**

So, if you have any questions or suggestions, do let me know here in the comment section below.

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